industrial temperature range idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs 1 january 2003 idt74auc164245 industrial temperature range cmos 16-bit level shifting bus transceiver with 3-state outputs description: this 16-bit level shifting bus transceiver is built using advanced cmos technology. the auc164245 is ideal for asynchronous communications between data buses. the control function implementation minimizes external timing requirements. the auc164245 16-bit level shifting bus transceiver contains two separate supply rails. the b port is designed to track v ddb , which accepts voltages from 0.8v to 2.7v. the a port and control inputs are designed to track v dda , which accepts voltages from 0.8v to 2.7v. this allows for user-selectable translation for various level shifting system environments. this device can be used as one 16-bit transceiver or two 8-bit transceivers. it allows data transmission from a bus to b bus or from b bus to a bus, depending on the logic level at the direction-control (dir) input. the output-enable ( oe ) input can be used to disable the device so that the buses are effectively isolated. this device is fully specified for partial power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. the auc164245 a and b ports are designed with 9ma output drivers. these drivers are capable of driving moderate loads while maintaining high speed performance. to ensure the high-impedance state during power up or power down, oe should be tied to v dda through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1 dir 1 a 1 1 a 2 1 a 3 1 a 4 1 a 5 1 a 6 1 a 7 1 a 8 1 b 8 1 b 7 1 b 6 1 b 5 1 b 4 1 b 3 1 b 2 1 b 1 1 oe 2 dir 2 a 1 2 a 2 2 a 3 2 a 4 2 a 5 2 a 6 2 a 7 2 a 8 2 b 8 2 b 7 2 b 6 2 b 5 2 b 4 2 b 3 2 b 2 2 b 1 2 oe 1 47 46 44 43 41 40 38 37 12 11 9 8 6 5 3 2 48 24 36 35 33 32 30 29 27 26 23 22 20 19 17 16 14 13 25 0 . 8 v - 2 . 7 v 0 . 8 v - 2 . 7 v 0 . 8 v - 2 . 7 v 0 . 8 v - 2 . 7 v the idt logo is a registered trademark of integrated device technology, inc. ? 2003 integrated device technology, inc. dsc-5970/20 features: ?v dda and v ddb = 0.8v - 2.7v ? inputs/outputs tolerant up to 3.6v ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? supports hot insertion: ? a and b port output drivers: 9ma @ 2.3v ? available in tssop, tvsop, and vfbga packages functional block diagram applications: ? high performance, low voltage communications systems ? high performance, low voltage computing systems
industrial temperature range 2 idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs a 1oe nc nc nc nc 1dir b 1a2 1a1 gnd gnd 1b1 1b2 c 1a4 1a3 v dda v ddb 1b3 1b4 e 1a8 1a7 1b7 1b8 f 2a1 2a2 2b2 2b1 g 2a3 2a4 gnd gnd 2b4 2b3 h 2a5 2a6 2b6 2b5 j 2a7 2a8 gnd gnd 2b8 2b7 k 2oe 2dir nc nc nc nc d 1a6 1a5 gnd gnd 1b5 1b6 6 5 4 3 2 1 v dda v ddb 6 5 4 3 2 1 abcdefghj k vfbga 56 ball vfbga package layout pinout configuration top view note: nc = no internal connection
industrial temperature range idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs 3 tssop/ tvsop top view pin configuration 1 dir 1 b 1 1 b 2 gnd 1 b 3 1 b 4 1 b 5 1 b 6 gnd 1 b 7 1 b 8 2 b 1 2 b 2 2 b 4 2 dir gnd 2 b 5 2 b 6 gnd 2 b 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 41 42 43 44 45 46 47 48 1 1 oe 1 a 1 1 a 2 gnd 1 a 3 1 a 4 v dda 1 a 5 1 a 6 1 a 7 1 a 8 2 a 1 gnd 2 a 3 2 a 4 2 a 5 2 a 6 gnd 2 a 7 2 a 8 2 oe 2 b 3 2 b 8 2 a 2 gnd v dda v ddb v ddb absolute maximum ratings for v dda or v ddb (1) symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +3.6 v (all input and v dd terminals) v term terminal voltage with respect to gnd ?0.5 to +3.6 v (any i/o or output terminals in high- impedance or power-off state) v term terminal voltage with respect to gnd ?0.5 to +3.6 v (any i/o or output terminals in high or low state) t stg storage temperature ?65 to +150 c i out continuous dc output current 20 ma i ik continuous clamp v i > v dd +50 ma current v i < 0 ?50 i ok continuous clamp current, v o < 0 ?50 ma i dd continuous current through 100 ma i ss each v dd or gnd note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. pin description pin names description x oe 3-state output enable control inputs (active low) (1) xdir direction control inputs (1) x a x a side inputs or 3-state outputs (1) x b x b side inputs or 3-state outputs (2) v dda supply for a port, x oe , xdir v ddb supply for b port function table (each 8-bit section) (1) note: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance inputs x oe xdir outputs l l bus b data to bus a l h bus a data to bus b hxz symbol parameter conditions typ. max. unit c in input capacitance (1) v in = v dd or gnd 2.5 4 pf c i/o i/o port capacitance (2) v i/o = v dd or gnd 6 7 pf capacitance (t a = +25c, f = 1.0mhz, v dda or v ddb = 2.5v) notes: 1. applies to the control inputs. 2. applies to ports a and b. notes: 1. powered from v dda . 2. powered from v ddb .
industrial temperature range 4 idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs symbol (2) parameter test conditions (2) min. (2) max. (2) unit v ddx supply voltage 0.8 2.7 v v ddx = 0.8v v ddx ? v ddx = 1.1v to 1.3v 0.65 x v ddx ? v ih (3) input high voltage level v ddx = 1.4v to 1.6v 0.65 x v ddx ?v v ddx = 1.65v to 1.95v 0.65 x v ddx ? v ddx = 2.3v to 2.7v 1.7 ? v ddx = 0.8v ? 0 v ddx = 1.1v to 1.3v ? 0.35 x v ddx v il (3) input low voltage level v ddx = 1.4v to 1.6v ? 0.35 x v ddx v v ddx = 1.65v to 1.95v ? 0.35 x v ddx v ddx = 2.3v to 2.7v ? 0.7 v i input voltage 0 2.7 v v o output voltage active state 0 v ddx v 3-state 0 2.7 v ddx = 0.8v ? ?0.7 v ddx = 1.1v ? ?3 i oh high level output current v ddx = 1.4v ? ?5 ma v ddx = 1.65v ? ?8 v ddx = 2.3v ? ?9 v ddx = 0.8v ? 0.7 v ddx = 1.1v ? 3 i ol low level output current v ddx = 1.4v ? 5 ma v ddx = 1.65v ? 8 v ddx = 2.3v ? 9 ? t/ ? v input transition rise or fall time ? 5 ns/v t a operating free-air temperature ?40 +85 c recommended operating characteristics (1) notes: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation. 2. where v ddx refers to either v dda or v ddb , depending on which side output a or b is on. 3. v il ,v ih limits apply for outputs operating at adjacent voltage ranges. for example, 1.8v v il /v ih limits apply for outputs operating at 1.5v or 2.5v.
industrial temperature range idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs 5 symbol parameter test conditions (2) min. (2) typ. (2) max. (2) unit i ih input high or low current data inputs v ddx = 2.7v, v i = v ddx or gnd ? ? 10 a i il control inputs ? ? 5 i off input/output power off leakage v ddx = 0v, v in or v o 2.7v ? ? 10 a i ozh (3) high impedance output current v ddx = 2.7v v o = v ddx ? ? 10 a i ozl (3) (3-state output pins) v o = gnd ? ? 10 i ddl quiescent power supply current v ddx = 0.8v to 2.7v ? ? 20 a i ddh v in = gnd or v ddx i ddz dc electrical characteristics over operating range (a port or b port) (1) following conditions apply unless otherwise specified: operating conditions: t a = ?40c to +85c notes: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation. 2. where v ddx refers to either v dda or v ddb , depending on which side output a or b is on. 3. for the i/o ports, the parameters i ozh and i ozl include the input leakage current. output drive characteristics (a port or b port) notes: 1. v il and v ih must be within the min. or max. range shown in the dc electrical characteristics table for the appropriate v dd range. t a = -40c to +85c. 2. demonstrates operation for nominal v dda or v ddb = 1.2v. 3. demonstrates operation for nominal v dda or v ddb = 1.5v. 4. demonstrates operation for nominal v dda or v ddb = 1.8v. 5. demonstrates operation for nominal v dda or v ddb = 2.5v. 6. where v ddx refers to either v dda or v ddb , depending on which side output a or b is on. symbol parameter test conditions (1,6) min. (6) typ. max. (6) unit v ddx = 0.8v - 2.7v i oh = ?100 av ddx - 0.1 ? ? v ddx = 0.8v i oh = ?0.7ma ? 0.55 ? v oh output high voltage v ddx = 1.1v (2) i oh = ?3ma 0.8 ? ? v v ddx = 1.4v (3) i oh = ?5ma 1 ? ? v ddx = 1.65v (4) i oh = ?8ma 1.2 ? ? v ddx = 2.3v (5) i ol = ?9ma 1.8 ? ? v ddx = 0.8v - 2.7v i ol = 100 a ? ? 0.2 v ddx = 0.8v i ol = 0.7ma ? 0.25 ? v ol output low voltage v ddx = 1.1v (2) i ol = 3ma ? ? 0.3 v v ddx = 1.4v (3) i ol = 5ma ? ? 0.4 v ddx = 1.65v (4) i ol = 8ma ? ? 0.45 v ddx = 2.3v (5) i ol = 9ma ? ? 0.6
industrial temperature range 6 idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs notes: 1. see test circuits and waveforms. t a = -40c to +85c. 2. the temperature range for the 0.8v node is 0c to +85c. 3. propagation delay is symmetrical a-b, depending only on input and output v dd . 4. enable/disable to xax depends on v dda only. times for xbx same if v dda = v ddb . operating characteristics, a to b, v dda and v ddb = 2.5v, t a = 25c symbol parameter test conditions typ. unit c pda power dissipation capacitance outputs enabled c l = 0pf 3 pf outputs disabled f = 10mhz 0.4 c pdb power dissipation capacitance outputs enabled c l = 0pf 1.4 pf outputs disabled f = 10mhz 1.5 operating characteristics, b to a, v dda and v ddb = 2.5v, t a = 25c symbol parameter test conditions typ. unit c pda power dissipation capacitance outputs enabled c l = 0pf 14 pf outputs disabled f = 10mhz 1.5 c pdb power dissipation capacitance outputs enabled c l = 0pf 3 pf outputs disabled f = 10mhz 0.4 switching characteristics, v dda = 0.8 (1,2) v ddb = 0.8v v ddb = 1.2v0.1v symbol parameter typ. typ. unit t plh propagation delay (3) 10 5 ns t phl xax to xbx t plh propagation delay (3) 10 11 ns t phl xbx to xax t pzh output enable time (4) 7.5 7.5 ns t pzl x oe to xax t phz output disable time (4) 8.5 8.5 ns t plz x oe to xax t pzh output enable time 10.5 4.8 ns t pzl x oe to xbx t phz output disable time 12 6.8 ns t plz x oe to xbx switching characteristics, v dda = 1.2v 0.1 (1) v ddb = 0.8v v ddb = 1.2v0.1v v ddb = 1.5v0.1v v ddb = 1.8v0.15v v ddb = 2.5v0.2v symbol parameter typ. min. max. min. max. min. typ. max. min. max. unit t plh propagation delay (3) 11 1 4.5 0.5 3.5 0.5 2 3.5 0.5 3 ns t phl xax to xbx t plh propagation delay (3) 5 1 4.5 0.5 4.5 0.5 3 4.2 0.5 4 ns t phl xbx to xax t pzh output enable time (4) 3.2 0.7 4.6 0.7 4.6 0.7 3.2 4.6 0.7 4.6 ns t pzl x oe to xax t phz output disable time (4) 4.6 0.8 6.2 0.8 6.2 0.8 4.6 6.2 0.8 6.2 ns t plz x oe to xax t pzh output enable time 9 0.7 4.6 (4) 0.7 3.6 0.7 2.2 3.6 0.7 3.5 ns t pzl x oe to xbx t phz output disable time 9.5 0.8 6.2 (4) 0.8 5 0.8 3.5 4.8 0.8 4.3 ns t plz x oe to xbx
industrial temperature range idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs 7 switching characteristics, v dda = 1.8v 0.15 (1) switching characteristics, v dda = 2.5v 0.2 (1) switching characteristics, v dda = 1.5v 0.1 (1) v ddb = 1.2v0.1v v ddb = 1.5v0.1v v ddb = 1.8v0.15v v ddb = 2.5v0.2v symbol parameter min. max. min. max. min. typ. max. min. max. unit t plh propagation delay (2) 0.5 4.2 0.5 3 0.5 2 2.8 0.5 2.5 ns t phl xax to xbx t plh propagation delay (2) 0.5 3.5 0.5 3.1 0.5 2 2.8 0.5 2.6 ns t phl xbx to xax t pzh output enable time (3) 0.7 3 0.7 3 0.7 2.1 3 0.7 3 ns t pzl x oe to xax t phz output disable time (3) 0.8 4.3 0.8 4.3 0.8 3.2 4.3 0.8 4.3 ns t plz x oe to xax t pzh output enable time 0.7 4 0.7 3 0.7 2.1 (3) 3 (3) 0.7 2.8 ns t pzl x oe to xbx t phz output disable time 0.8 5.3 0.8 4.3 0.8 3.2 (3) 4.3 (3) 0.8 3 ns t plz x oe to xbx v ddb = 1.2v0.1v v ddb = 1.5v0.1v v ddb = 1.8v0.15v v ddb = 2.5v0.2v symbol parameter min. max. min. max. min. typ. max. min. max. unit t plh propagation delay (2) 0.5 4.5 0.5 3.3 0.5 2.3 3.1 0.5 2.6 ns t phl xax to xbx t plh propagation delay (2) 0.5 3.5 0.5 3.3 0.5 2 3 0.5 2.8 ns t phl xbx to xax t pzh output enable time (3) 0.7 3.3 0.7 3.1 0.7 2.3 3.3 0.7 3.3 ns t pzl x oe to xax t phz output disable time (3) 0.8 4.5 0.8 4.7 0.8 3 4.5 0.8 4.5 ns t plz x oe to xax t pzh output enable time 0.7 4.3 0.7 3.1 (3) 0.7 2.3 3.3 0.7 3.2 ns t pzl x oe to xbx t phz output disable time 0.8 5.5 0.8 4.7 (3) 0.8 3 4.5 0.8 3.7 ns t plz x oe to xbx v ddb = 1.2v0.1v v ddb = 1.5v0.1v v ddb = 1.8v0.15v v ddb = 2.5v0.2v symbol parameter min. max. min. max. min. typ. max. min. max. unit t plh propagation delay (2) 0.5 4 0.5 2.8 0.5 1.8 2.6 0.5 2.2 ns t phl xax to xbx t plh propagation delay (2) 0.5 3 0.5 2.6 0.5 1.7 2.5 0.5 2.2 ns t phl xbx to xax t pzh output enable time (3) 0.7 2.6 0.7 2.6 0.7 1.8 2.6 0.7 2.6 ns t pzl x oe to xax t phz output disable time (3) 0.8 2.9 0.8 2.9 0.8 2 2.9 0.8 2.9 ns t plz x oe to xax t pzh output enable time 0.7 4 0.7 2.8 0.7 2 3.1 0.7 2.6 (3) ns t pzl x oe to xbx t phz output disable time 0.8 5.3 0.8 4.1 0.8 3 4.3 0.8 2.9 (3) ns t plz x oe to xbx notes: 1. see test circuits and waveforms. t a = -40c to +85c. 2. propagation delay is symmetrical a-b, depending only on input and output v dd . 3. enable/disable to xax depends on v dda only. times for xbx same if v dda = v ddb .
industrial temperature range 8 idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs test circuits and waveforms open v load gnd v dd pulse generator d.u.t. r l c l r t v in v out (1) same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ddx v t v t v ddx v t control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol + v lz v oh v t v t t pzl v load/2 v load/2 v ddx v t v ol v oh - v hz r l (2) (2) (2) propagation delay test circuits for all outputs enable and disable times notes: 1. diagram shown for input control enable-low and input control disable-high. 2. where v ddx refers to either v dda or v ddb definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test switch open drain disable low v load enable low disable high gnd enable high all other tests open switch position symbol v ddx (1) = 0.8v v ddx (1) = 1.2v0.1v v ddx (1) = 1.5v0.1v v ddx (1) = 1.8v0.15v v ddx (1) = 2.5v0.2v unit v load 2xv dd x (1) 2xv dd x (1) 2xv dd x (1) 2xv dd x (1) 2xv dd x (1) v v t v ddx /2 (1) v ddx /2 (1) v ddx /2 (1) v ddx /2 (1) v ddx /2 (1) v v lz 100 100 100 100 150 mv v hz 100 100 100 100 150 mv r l 2 2 2 1 0.5 k ? c l 15 15 15 30 30 pf note: 1. where v ddx refers to either v dda or v ddb . note: 1. pulse generator for all pulses: rate 10mhz; slew rate 1v/ns.
industrial temperature range idt74auc164245 cmos 16-bit level shifting bus transceiver with 3-state outputs 9 ordering information idt xx auc xxx device type temp. range 16 74 4245 blank bv pa pf 16-bit level shifting bus transceiver with 3-state outputs ? 40c to +85c xx family double-density no bus-hold x bus-hold xx package very fine pitch ball grid array thin shrink small outline package thin very small outline package x grade i industrial temperature range corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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